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24-bit, 8.5 mw, 109 db, 128 ksps/64 ksps/32 ksps adcs AD7767 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007C2010 analog devices, inc. all rights reserved. features oversampled successive approximation (sar) architecture high performance ac and dc accuracy, low power 115.5 db dynamic range, 32 ksps (AD7767-2) 112.5 db dynamic range, 64 ksps (AD7767-1) 109.5 db dynamic range, 128 ksps (AD7767) ?118 db thd exceptionally low power 8.5 mw, 32 ksps (AD7767-2) 10.5 mw, 64 ksps (AD7767-1) 15 mw, 128 ksps (AD7767) high dc accuracy 24 bits, no missing codes (nmc) inl: 3 ppm (typical), 7.6 ppm (maximum) low temperature drift zero error drift: 15 nv/c gain error drift: 0.4 ppm/c on-chip low-pass fir filter linear phase response pass-band ripple: 0.005 db stop-band attenuation: 100 db 2.5 v supply with 1.8 v/2.5 v/3 v/3.6 v logic interface options flexible interfacing options synchronization of multiple devices daisy-chain capability power-down function temperature range: ?40c to +105c applications low power pci/usb data acquisition systems low power wireless acquisition systems vibration analysis instrumentation high precision medical acquisition functional block diagram v ref+ v in+ v in? refgnd av dd agnd mclk dv dd v drive dgnd successive approximation adc digital fir filter serial interface and control logic sclk drdy sdo sdi AD7767/ AD7767-1/ AD7767-2 cs sync/pd 06859-001 figure 1. general description the AD7767/AD7767-1/AD7767-2 are high performance, 24-bit, oversampled sar analog-to-digital converters (adcs). the AD7767/AD7767-1/AD7767-2 combine the benefits of a large dynamic range and input bandwidth, consuming 15 mw, 10.5 mw, and 8.5 mw power, respectively, and are contained in a 16-lead tssop package. ideal for ultralow power data acquisition (such as pci- and usb-based systems), the AD7767/AD7767-1/AD7767-2 provide 24-bit resolution. the combination of exceptional snr, wide dynamic range, and outstanding dc accuracy make the AD7767/AD7767-1/AD7767-2 ideally suited for measuring small signal changes over a wide dynamic range. this is particularly suitable for applications where small changes on the input are measured on larger ac or dc signals. in such an application, the AD7767/AD7767-1/AD7767-2 accurately gather both ac and dc information. the AD7767/AD7767-1/AD7767-2 include an on-board digital filter (complete with linear phase response) that acts to elimi- nate out-of-band noise by filtering the oversampled input voltage. the oversampled architecture also reduces front-end antialias requirements. other features of the AD7767 include a sync / pd (synchronization/power-down) pin, allowing the synchronization of multiple AD7767 devices. the addition of an sdi pin provides the option of daisy chaining multiple AD7767 devices. the AD7767/AD7767-1/AD7767-2 operate from a 2.5 v supply using a 5 v reference. the devices operate from ?40c to +105c. related devices table 1. 24-bit adcs part no. description ad7760 2.5 msps, 100 db dynamic range, 1 on-board differential amp and reference buffer, parallel, variable decimation ad7762 / ad7763 625 ksps, 109 db dynamic range, 1 on-board differential amp and reference buffer, parallel/serial, variable decimation ad7764 312 ksps, 109 db dynamic range, 1 on-board differential amp and reference buffer, variable decimation (pin) ad7765 156 ksps, 112 db dynamic range, 1 on-board differential amp and reference buffer, variable decimation (pin) ad7766 128 ksps, 109.5 db, 1 15 mw, 16-bit inl, serial interface ad7766-1 64 ksps 112.5 db, 1 10.5 mw, 16-bit inl, serial interface ad7766-2 32 ksps, 115.5 db, 1 8.5 mw, 16-bit inl, serial interface 1 dynamic range at maximum output data rate.
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AD7767 rev. c | page 2 of 2 4 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? related devices ................................................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? timing specifications .................................................................. 5 ? timing diagrams .......................................................................... 6 ? absolute maximum ratings ............................................................ 8 ? esd caution .................................................................................. 8 ? pin configuration and function descriptions ............................. 9 ? typical performance characteristics ........................................... 10 ? terminology .................................................................................... 14 ? theory of operation ...................................................................... 15 ? AD7767/AD7767-1/AD7767-2 transfer function ................ 15 ? converter operation .................................................................. 15 ? analog input structure .............................................................. 16 ? supply and reference voltages ................................................. 16 ? AD7767 interface ........................................................................... 17 ? initial power-up ......................................................................... 17 ? reading data ............................................................................... 17 ? power-down, reset, and synchronization ............................. 17 ? daisy chaining ............................................................................... 18 ? reading data in daisy-chain mode ....................................... 18 ? choosing the sclk frequency ................................................ 18 ? daisy-chain mode configuration and timing diagrams ... 19 ? driving the AD7767 ....................................................................... 20 ? differential signal source ......................................................... 20 ? single-ended signal source ...................................................... 20 ? antialiasing ................................................................................. 21 ? power dissipation....................................................................... 21 ? v ref+ input signal ....................................................................... 22 ? multiplexing analog input channels ...................................... 22 ? outline dimensions ....................................................................... 23 ? ordering guide .......................................................................... 23 ? revision history 5/10rev. b to rev. c changes to pin 8 description ......................................................... 9 changes to table 8 .......................................................................... 20 3/09rev. a to rev. b changes to t settling parameter, table 3 .......................................... 5 changes to table 7 .......................................................................... 17 1/09rev. 0 to rev. a changes to features section............................................................ 1 change to intermodulation distortion (imd) parameter and integral nonlinearity parameter, table 2 ................................. 3 changes to supply and reference voltages section ................... 16 changes to choosing the sclk frequency section .................. 18 changes to figure 24 ...................................................................... 12 changes to driving the AD7767 section .................................... 20 changes to single-ended signal source section ........................ 20 added figure 41; renumbered sequentially .............................. 20 change to figure 42 ....................................................................... 21 added table 8; renumbered sequentially .................................. 20 replaced v ref+ input signal section ............................................ 22 replaced figure 46 ......................................................................... 22 8/07revision 0: initial version
AD7767 rev. c | page 3 of 24 specifications av dd = dv dd = 2.5 v 5%, v drive = 1.8 v to 3.6 v, v ref = 5 v, mclk = 1 mhz, common-mode input = v ref /2, t a = ?40c to +105c, unless otherwise noted. table 2. parameter test conditions/comments min typ max unit output data rate (odr) AD7767 decimate by 8 128 khz AD7767-1 decimate by 16 64 khz AD7767-2 decimate by 32 32 khz analog input 1 differential input voltage v in+ ? v in? v ref v p-p absolute input voltage v in+ ?0.1 +v ref + 0.1 v v in? ?0.1 +v ref + 0.1 v common-mode input voltage v ref /2 ? 5% v ref /2 v ref /2 + 5% v input capacitance 22 pf dynamic performance AD7767 decimate by 8, odr = 128 khz dynamic range 2 shorted inputs 108 109.5 db signal-to-noise ratio (snr) 2 full-scale input amplitude, 1 khz tone 107 108.5 db spurious-free dynamic range (sfdr) 2 full-scale input amplitude, 1 khz tone ?128 ?116 db total harmonic distortion (thd) 2 full-scale input amplitude, 1 khz tone ?118 ?105 db intermodulation distortion (imd) 2 tone a = 49.7 khz, tone b = 50.3 khz second-order terms ?133 db third-order terms ?109 db AD7767-1 decimate by 16, odr = 64 khz dynamic range 2 shorted inputs 111 112.5 db signal-to-noise ratio (snr) 2 full-scale input amplitude, 1 khz tone 110 111.5 db spurious-free dynamic range (sfdr) 2 full-scale input amplitude, 1 khz tone ?128 ?116 db total harmonic distortion (thd) 2 full-scale input amplitude, 1 khz tone ?118 ?105 db intermodulation distortion (imd) 2 tone a = 24.7 khz, tone b = 25.3 khz db second-order terms ?133 db third-order terms ?108 db AD7767-2 decimate by 32, odr = 32 khz dynamic range 2 shorted inputs 114 115.5 db signal-to-noise ratio (snr) 2 full-scale input amplitude, 1 khz tone 112 113.5 db spurious-free dynamic range (sfdr) 2 full-scale input amplitude, 1 khz tone ?128 ?116 db total harmonic distortion (thd) 2 full-scale input amplitude, 1 khz tone ?118 ?105 db intermodulation distortion (imd) 2 tone a = 11.7 khz, tone b = 12.3 khz db second-order terms ?137 db third-order terms ?108 db dc accuracy 1 for all devices resolution no missing codes 24 bits differential nonlinearity 2 guaranteed monotonic to 24 bits integral nonlinearity 2 18-bit linearity 3 7.6 ppm zero error 2 20 v gain error 2 0.0075 0.075 % fs zero error drift 2 15 nv/c gain error drift 2 0.4 ppm/c common-mode rejection ratio 2 50 hz tone ?110 db
AD7767 rev. c | page 4 of 2 4 parameter test conditions/comments min typ max unit digital filter response 1 group delay 37/odr s settling time (latency) comp lete settling 74/odr s pass-band ripple 0.005 db pass band 0.453 odr hz ?3 db bandwidth 0.49 odr hz stop-band frequency 0.547 odr hz stop-band attenuation 100 db reference input 1 v ref+ input voltage 2.4 2 av dd v digital inputs (logic levels) 1 v il ?0.3 +0.3 v drive v v ih 0.7 v drive v drive + 0.3 v input leakage current 1 a/pin input capacitance 5 pf master clock rate 1.024 mhz serial clock rate 1/t 8 hz digital outputs 1 data format serial 24 bits, twos complement (msb first) v ol i sink = +500 a 0.4 v v oh i source = ?500 a v drive C 0.3 v power requirements 1 av dd 5% 2.5 v dv dd 5% 2.5 v v drive 1.7 2.5 3.6 v current specifications mclk = 1.024 mhz AD7767 operational current 128 khz output data rate ai dd 1.3 1.5 ma di dd 3.9 4.8 ma i ref 0.35 0.425 ma AD7767-1 operational current 64 khz output data rate ai dd 1.3 1.5 ma di dd 2.2 2.85 ma i ref 0.35 0.425 ma AD7767-2 operational current 32 khz output data rate ai dd 1.3 1.5 ma di dd 1.37 1.86 ma i ref 0.35 0.425 ma static current with mclk stopped for all devices ai dd 0.9 1 ma di dd 1 93 a power-down mode current for all devices ai dd 0.1 6 a di dd 1 93 a power dissipation mclk = 1.024 mhz AD7767 operational power 128 khz output data rate 15 18 mw AD7767-1 operational power 64 khz output data rate 10.5 13 mw AD7767-2 operational power 32 khz output data rate 8.5 10.5 mw 1 specifications are for all devi ces, AD7767, AD7767-1, and AD7767-2. 2 see the terminology section.
AD7767 rev. c | page 5 of 24 timing specifications av dd = dv dd = 2.5 v 5%, v drive = 1.7 v to 3.6 v, v ref = 5 v, common-mode input = v ref /2, t a = ?40c (t min ) to +105c (t max ), unless otherwise noted. 1 table 3. parameter limit at t min , t max unit description drdy operation t 1 510 ns typ mclk rising edge to drdy falling edge t 2 2 100 ns min mclk high pulse width t 3 2 900 ns max mclk low pulse width t 4 265 ns typ mclk rising edge to drdy rising edge (AD7767) 128 ns typ mclk rising edge to drdy rising edge (AD7767-1) 71 ns typ mclk rising edge to drdy rising edge (AD7767-2) t 5 294 ns typ drdy pulse width (AD7767) 435 ns typ drdy pulse width (AD7767-1) 492 ns typ drdy pulse width (AD7767-2) t read 3 t drdy ? t 5 ns typ drdy low period, read data during this period t drdy 3 n 8 t mclk ns typ drdy period read operation t 6 0 ns min drdy falling edge to cs setup time t 7 6 ns max cs falling edge to sdo tristate disabled t 8 60 ns max data access time after sclk falling edge (v drive = 1.7 v) 50 ns max data access time after sclk falling edge (v drive = 2.3 v) 25 ns max data access time after sclk falling edge (v drive = 2.7 v) 24 ns max data access time after sclk falling edge (v drive = 3.0 v) t 9 10 ns min sclk falling edge to data valid hold time (v drive = 3.6 v) t 10 10 ns min sclk high pulse width t 11 10 ns min sclk low pulse width t sclk 1/t 8 sec min minimum sclk period t 12 6 ns max bus relinquish time after cs rising edge t 13 0 ns min cs rising edge to drdy rising edge read operation with cs low t 14 0 ns min drdy falling edge to data valid setup time t 15 0 ns max drdy rising edge to data valid hold time daisy-chain operation t 16 1 ns min sdi valid to sclk falling edge setup time t 17 2 ns max sclk falling edge to sdi valid hold time sync / pd operation t 18 1 ns typ sync / pd falling edge to mclk rising edge t 19 20 ns typ mclk rising edge to drdy rising edge going into sync / pd mode t 20 1 ns min sync / pd rising edge to mclk rising edge t 21 510 ns typ mclk rising edge to drdy falling edge coming out of sync / pd mode t settling 3 (592 n) + 2 t mclk filter settling time after a reset or power-down 1 sample tested during initial release to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of dv dd ) and timed from a voltage level of 1.7 v. 2 t 2 and t 3 allow a ~90% to 10% duty cycle to be used for the mclk input, where the minimum is 10% for the clock high time and 90% for mcl k low time. the maximum mclk frequency is 1.024 mhz. 3 n = 1 for AD7767, n = 2 for the AD7767-1, n = 4 for the AD7767-2.
AD7767 rev. c | page 6 of 24 timing diagrams mclk 1 drdy t 2 t 3 t 4 t 1 t read t 5 t 5 t drdy 8 n 8 n 1 06859-002 figure 2. drdy vs. mclk timing diagram, n = 1 for AD7767 (decimate by 8), n = 2 for AD7767-1 (decimate by 16), n = 4 for AD7767-2 (decimate b y 32) 06859-003 drdy cs sclk sdo t drdy t read d22 msb d21 d20 d1 lsb t 6 t 13 t 12 1 23 t 10 t 11 t 7 t 8 t 9 figure 3. serial timing diagram, reading data using cs 06859-004 cs = 0 sclk sdo data invalid msb d22 d21 d20 d1 lsb data invalid drdy t drdy t read 1 23 24 t 14 t 8 t 9 t 15 t 11 t 10 figure 4. serial timing diagram, reading data setting cs logic low
AD7767 rev. c | page 7 of 24 06859-005 mclk (i) s ync/pd (i) drdy ( o ) dout (o) invalid data valid data valid data t 18 t settling t 19 t 20 part in power-down part out of power-down filter reset begins sampling ab c d t 21 figure 5. reset, synchronization, and power-down timing (for more information, see the power-down, reset, and synchronization section)
AD7767 rev. c | page 8 of 24 absolute maximum ratings t a = 25c, unless otherwise noted. table 4. parameter rating av dd to agnd ?0.3 v to +3 v dv dd to dgnd ?0.3 v to +3 v av dd to dv dd ?0.3 v to +0.3 v v ref+ to refgnd ?0.3 v to +7 v refgnd to agnd ?0.3 v to +0.3 v v drive to dgnd ?0.3 v to +6 v v in+ , v inC to agnd ?0.3 v to v ref+ + 0.3 v digital inputs to dgnd ?0.3 v to v drive + 0.3 v digital outputs to dgnd ?0.3 v to v drive + 0.3 v agnd to dgnd ?0.3 v to +0.3 v input current to any pin except supplies 1 10 ma operating temperature range ?40c to +105c storage temperature range ?65c to +150c junction temperature 150c tssop package ja thermal impedance 150.4c/w jc thermal impedance 27.6c/w lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c esd 1 kv stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution 1 transient currents of up to 100 ma do not cause scr latch-up.
AD7767 rev. c | page 9 of 24 pin configuration and fu nction descriptions 06859-006 1 2 3 4 5 6 7 8 v ref+ refgnd v in+ s ync/pd agnd v in? av dd dv dd 16 15 14 13 12 11 10 9 sdi mclk sclk sdo v drive dgnd drdy cs AD7767/ ad767-1/ AD7767-2 top view (not to scale) figure 6. 16-lead tssop pin configuration table 5. pin function descriptions pin no. mnemonic description 1 av dd +2.5 v analog power supply. 2 v ref+ reference input for the AD7767. an external refere nce must be applied to this input pin. the v ref+ input can range from 2.4 v to 5 v. the reference voltage input is in dependent of the voltage magnitude applied to the av dd pin. 3 refgnd reference ground. ground connection for the reference voltage. the input reference voltage (v ref+ ) should be decoupled to this pin. 4 v in+ positive input of the differential analog input. 5 v in? negative input of the differential analog input. 6 agnd power supply ground for analog circuitry. 7 sync / pd synchronization and power-down input pin. this pin has dual functionality. it can be used to synchronize multiple AD7767 devices and/or to put the AD7767 device into power-down mode. see the power-down, reset, and synchronization section for further details. 8 dv dd 2.5 v digital power supply input. in cases where an logic vo ltage of 2.5 v is used for interfacing (2.5 v applied to v drive pin), the dvdd and v drive pin may be connected to the same voltage supply rail. 9 v drive logic power supply input, 1.8 v to 3.6 v. the voltage supp lied at this pin determines the operating voltage of the digital logic interface. 10 sdo serial data output. the conversion result from the AD7767 is output on the sdo pin as a 24-bit, twos complement, msb first, serial data stream. 11 dgnd digital logic power supply ground. 12 drdy data ready output. a falling edge on the drdy signal indicates that a new conversion data result is available in the output register of the AD7767. see the section for further details. AD7767 interface 13 sclk serial clock input. the sclk input provides the serial cl ock for all serial data transfers with the AD7767 device. see the AD7767 interface section for further details. 14 mclk master clock input. the AD7767 sampling frequency is equal to the mclk frequency. 15 sdi serial data input. this is the daisy-chain input of the AD7767. see the daisy chaining section for further details. 16 cs chip select input. the cs input selects the AD7767 device and acts as an enable on the sdo pin. in cases where cs is used, the msb of the conversion result is clocked onto the sdo line on the cs falling edge. the cs input allows multiple AD7767 devices to share the same sdo line. this allows the user to select the appropriate device by supplying it with a logic low cs signal, which enables the sdo pin of the device concerned. see the section for further details. AD7767 interface
AD7767 rev. c | page 10 of 24 typical performance characteristics av dd = dv dd = 2.5 v 5%, v drive = 1.8 v to 3.6 v, v ref = 5 v, mclk = 1 mhz, common-mode input = v ref /2. t a = 25c, unless otherwise noted. all ffts were generated using 8192 samples using a four-term blackman-harris window. 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 0 8k 16k 24k 32k 40k 48k 56k 64k amplitude (db) frequency (hz) 06859-101 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 0 8k 16k 24k 32k 40k 48k 56k 64k amplitude (db) frequency (hz) 06859-104 figure 10. AD7767 fft, 1 khz, ?6 db input tone figure 7. AD7767 fft, 1 khz, ?0.5 db input tone 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 0 4k 8k 12k 16k 20k 24k 28k 32k amplitude (db) frequency (hz) 06859-105 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 0 4k 8k 12k 16k 20k 24k 28k 32k amplitude (db) frequency (hz) 06859-102 figure 11. AD7767-1 fft, 1 khz, ?6 db input tone figure 8. AD7767-1 fft, 1 khz, ?0.5 db input tone 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 01 6 k 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 01 12k 8k 4k amplitude (db) frequency (hz) 6 k 06859-106 12k 8k 4k amplitude (db) frequency (hz) 06859-103 figure 12. AD7767-2 fft, 1 khz, ?6 db input tone figure 9. AD7767-2 fft, 1 khz, ?0.5 db input tone
AD7767 rev. c | page 11 of 24 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 0 8k 16k 24k 32k 40k 48k 56k 64k amplitude (db) frequency (hz) 06859-107 figure 13. AD7767 fft, 1 khz, ?60 db input tone 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 0 4k 8k 12k 16k 20k 24k 28k 32k amplitude (db) frequency (hz) 06859-108 figure 14. AD7767-1 fft, 1 khz, ?60 db input tone 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 01 6 k 12k 8k 4k amplitude (db) frequency (hz) 06859-109 figure 15. AD7767-2 fft, 1 khz, ?60 db input tone 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 0 8k 16k 24k 32k 40k 48k 56k 64k amplitude (db) frequency (hz) tone a = 49.7khz tone b = 50.3khz second-order imd = ?133.71db third-order imd = ?109.05db 06859-110 figure 16. AD7767 imd fft, 50 khz center frequency 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 0 4k 8k 12k 16k 20k 24k 28k 32k amplitude (db) frequency (hz) tone a = 24.7khz tone b = 25.3khz second-order imd = ?133.33db third-order imd = ?108.15db 06859-111 figure 17. AD7767-1 imd fft, 25 khz center frequency 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 01 12k 8k 4k amplitude (db) frequency (hz) 6 k tone a = 11.7khz tone b = 12.3khz second-order imd = ?137.96db third-order imd = ?108.1db 06859-112 figure 18. AD7767-2 imd fft, 12 khz center frequency
AD7767 rev. c | page 12 of 2 4 ? 110 ?130 ?128 ? 126 ?124 ?122 ?120 ?118 ?116 ?114 ?112 01 900k 800k 700k 600k 500k 400k 300k 200k 100k thd (db) mclk frequency (hz) 06859-113 m AD7767 AD7767-1 AD7767-2 figure 19. AD7767/AD7767-1/AD7767-2 thd vs. mclk frequency 06859-114 115 107 108 109 110 111 112 113 114 01 m 900k 800k 700k 600k 500k 400k 300k 200k 100k snr (db) mclk frequency (hz) AD7767 AD7767-1 AD7767-2 figure 20. AD7767/AD7767-1/AD7767-2 snr vs. mclk frequency 150 140 130 120 110 100 06 50k 40k 30k 20k 10k psrr (db) f noise (hz) av dd dv dd v drive 0 k 06859-117 figure 21. AD7767 power supply sensitivity vs. supply ripple frequency (f noise ) with decoupling capacitors 120 115 110 105 100 95 90 06 50k 40k 30k 20k 10k cmrr (db) f noise (hz) 0 k open inputs full-scale 921hz dynamic range 06859-116 figure 22. AD7767 cmrr vs. common-mode ripple frequency (f noise ) 200 160 120 80 40 180 140 100 60 20 0 occurrence codes 8388493 8388497 8388501 8388505 8388509 8388513 8388517 8388521 8388525 8388529 8388533 8388537 8388541 8388545 8388549 8388553 8388557 8388561 8388565 8388569 8388573 8388577 8388581 8388585 8388589 8388593 8388597 8388601 8388605 8388609 8388613 8388617 8388621 8388625 8388629 8388633 8388637 max = 8388637 min = 8388493 spread = 145 06859-118 figure 23. AD7767 24-bit histogram 250 200 150 100 50 0 occurrence codes max = 8388608 min = 8388507 spread = 102 codes 8388508 8388512 8388516 8388520 8388524 8388528 8388532 8388536 8388540 8388544 8388548 8388552 8388556 8388560 8388564 8388568 8388572 8388576 8388580 8388584 8388588 8388592 8388596 8388600 8388604 8388608 06859-119 figure 24. AD7767-1 24-bit histogram
AD7767 rev. c | page 13 of 24 3.80 ?3.80 ?3.04 ?2.28 ?1.52 ?0.76 0 0.76 1.52 2.28 3.04 0 2097152 4194304 6291456 8388608 10485760 12582912 14680064 16777216 inl (ppm) 24-bit codes low temperature nominal temperature high temperature 0 6859-122 350 300 250 200 150 100 50 0 occurrence codes max = 8388593 min = 8388526 spread = 69 codes 8388526 8388529 8388532 8388535 8388538 8388541 8388544 8388547 8388550 8388553 8388556 8388559 8388562 8388565 8388568 8388571 8388574 8388577 8388580 8388583 8388586 8388589 8388592 06859-120 figure 25. AD7767-2 24-bit histogram figure 27. AD7767/AD7767-1/AD7767-2 24-bit inl 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 2097152 4194304 6291456 8388608 10485760 12582912 14680064 16777216 dnl (lsbs) 24-bit codes 0 6859-121 figure 26. AD7767/AD7767-1/AD7767-2 24-bit dnl
AD7767 rev. c | page 14 of 24 terminology signal-to-noise ratio (snr) snr is the ratio of the actual input signals rms value to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. total harmonic distortion (thd) thd is the ratio of the rms sum of harmonics to the fundamen- tal. for the AD7767, it is defined as () 1 6 54 32 v vvvvv thd 22222 log20db ++++ = where: v 1 is the rms amplitude of the fundamental. v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second to the sixth harmonics. nonharmonic spurious-free dynamic range (sfdr) sfdr is the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component, excluding harmonics. dynamic range dynamic range is the ratio of the rms value of the full scale to the rms noise measured with the inputs shorted together. the value for the dynamic range is expressed in decibels. intermodulation distortion (imd) with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3, and so on. intermodulation distortion terms are those for which neither m nor n are equal to 0. for example, the second-order terms include (fa + fb) and (fa ? fb), and the third-order terms include (2fa + fb), (2fa ? fb), (fa + 2fb), and (fa ? 2fb). the AD7767 is tested using the ccif standard, where two input frequencies near the top end of the input bandwidth are used. in this case, the second-order terms are usually distanced in frequency from the original sine waves, and the third-order terms are usually at a frequency close to the input frequencies. as a result, the second- and third-order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels. integral nonlinearity (inl) inl is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. differential nonlinearity (dnl) dnl is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. zero error zero error is the difference between the ideal midscale input voltage (when both inputs are shorted together) and the actual voltage producing the midscale output code. zero error drift zero error drift is the change in the actual zero error value due to a temperature change of 1c. it is expressed as a percentage of full scale at room temperature. gain error the first transition (from 100 000 to 100 001) should occur ? lsb above the nominal negative full scale for an analog voltage. the last transition (from 011 110 to 011 111) should occur 1? lsb below the nominal full scale for an analog voltage. the gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition, from the difference between the ideal levels. gain error drift gain error drift is the change in the actual gain error value due to a temperature change of 1c. it is expressed as a percentage of full scale at room temperature. common-mode rejection ratio (cmrr) cmrr is defined as the ratio of the power in the adc output at full-scale frequency f to the power of a 100 mv sine wave applied to the common-mode voltage of the v in+ and v in? inputs at frequency f s . cmrr (db) = 10 log( pf / pf s ) where pf is the power at the frequency f in the adc output, and pf s is the power at the frequency f s in the adc output.
AD7767 rev. c | page 15 of 24 theory of operation the AD7767/AD7767-1/AD7767-2 operate using a fully differential analog input applied to a successive approximation (sar) core. the output of the oversampled sar is filtered using a linear-phase digital fir filter. the fully filtered data is output in a serial format, with the msb being clocked out first. AD7767/AD7767-1/AD7767-2 transfer function the conversion results of the AD7767/AD7767-1/AD7767-2 are output in a twos complement, 24-bit serial format. the fully differential inputs v in+ and v in? are scaled by the AD7767/ AD7767-1/AD7767-2 relative to the reference voltage input (v ref+ ) as shown in figure 28 . 06859-012 100 ... 000 100 ... 001 111 ... 110 111 ... 111 000 ... 000 000 ... 001 000 ... 010 011 ... 110 011 ... 111 24-bit output 24 bits twos complement v in+ = 0v v in+ = v ref ? 1lsb v in? = v ref ? 1lsb v in? = 0v v in+ = v ref 2 v in? = v ref 2 figure 28. AD7767/AD7767-1/AD7767-2 transfer function converter operation internally, the input waveform applied to the sar core is converted and an equivalent digital word is output to the digital filter at a rate equal to mclk. by employing oversampling, the quantization noise of the converter is spread across a wide bandwidth from 0 to f mclk . this means that the noise energy contained in the signal band of interest is reduced (see figure 29 ). quantization noise band of interest f mclk/2 06859-213 figure 29. quantization noise digital filter cutoff frequency f mclk/2 band of interest 0 6859-214 figure 30. digital filter cutoff frequency the digital filtering that follows the converter output acts to remove the out-of-band quantization noise (see figure 30 ). this also has the effect of reducing the data rate from f mclk at the input of the filter to f mclk /8, f mclk /16, or f mclk /32 at the digital output, depending on which model of the device is being used. the digital filter consists of three separate filter blocks. figure 31 shows the three constituent blocks of the filter. the order of decimation of the first filter block is set as 2, 4, or 8. the remaining sections each operate with a decimation of 2. 06859-019 stage 1 stage 2 digital filter stage 3 sinc filter fir filter fir filter dec (2 n) dec 2 dec 2 data s tream sdo figure 31. fir filter stages (n = 1 for AD7767, n = 2 for AD7767-1, n = 4 for AD7767-2) table 6 shows the three available models of the AD7767, listing the change in output data rate relative to the order of decimation rate implemented. this brings into focus the trade-off that exists between extra filtering and reduction in bandwidth, whereby using a filter option with a larger decimation rate increases the noise performance while decreasing the usable input bandwidth. table 6. AD7767 models model decimation rate output data rate (odr) AD7767 8 128 khz AD7767-1 16 64 khz AD7767-2 32 32 khz note that the output data rates shown in table 6 are realized when using the maximum mclk input frequency of 1.024 mhz. the output data rate scales linearly with the mclk frequency, as does the digital power dissipated in the device. the settling time of the filter implemented on the AD7767, AD7767-1, and AD7767-2 is related to the length of the filter employed. the response of the filter in the time domain sets the filter settling time. table 7 shows the filter settling times of the AD7767/AD7767-1/AD7767-2. the frequency responses of the digital filters on the AD7767, AD7767-1, and AD7767-2 are shown in figure 32 , figure 33 , and figure 34 , respectively. at the nyquist frequency (output data rate/2), the digital filter provides 6 db of attenuation. in each case, the filter provides stop-band attenuation of 100 db and pass-band ripple of 0.005 db.
AD7767 rev. c | page 16 of 24 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 0 128k 112k 96k 80k 64k 48k 32k 16k amplitude (db) frequency (hz) 06859-216 figure 32. AD7767 digital filter frequency response 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 0 64k 56k 48k 40k 32k 24k 16k 8k amplitude (db) frequency (hz) 06859-217 figure 33. AD7767-1 digital filter frequency response 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 0 32k 28k 24k 20k 16k 12k 8k4k amplitude (db) frequency (hz) 06859-218 figure 34. AD7767-2 digital filter frequency response analog input structure the AD7767/AD7767-1/AD7767-2 are configured as a differential input structure. a true differential signal is sampled between the analog inputs v in+ and v in? , pin 4 and pin 5, respectively. using differential inputs provides rejection of signals that are common to both the v in+ and v in? pins. figure 35 shows the equivalent analog input circuit of the AD7767/AD7767-1/AD7767-2. the two diodes on each of the differential inputs provide esd protection for the analog inputs. 06859-219 v in+ v ref+ c1 d d gnd agnd r in c2 v in? v ref+ c1 d d gnd agnd r in c2 figure 35. equivalent analog input structure take care to ensure that the analog input signal does not exceed the reference supply voltage (v ref+ ) by more than 0.3 v, as specified in the absolute maximum ratings section. if the input voltage exceeds this limit, the diodes become forward biased and start to conduct current. the diodes can handle 130 ma maximum. the impedance of the analog inputs can be modeled as a parallel combination of c1 and the network formed by the series con- nection of r in , c1, and c2. the value of c1 is dominated by the pin capacitance. r in is typically 1.4 k, the lumped component of serial resistors and the r on of the switches. c2 is typically 22 pf, and its value is dominated by the sampling capacitor. supply and refere nce voltages the AD7767/AD7767-1/AD7767-2 operate from a 2.5 v supply applied to the dv dd and av dd pins. the interface is specified to operate between 1.7 v and 3.6 v. the AD7767/AD7767-1/ AD7767-2 operate from a reference input in the range of 2.2 v to 2 av dd applied to the v ref+ pin. the nominal reference supply voltage is 5 v, but a 2.5 v supply can also be used. when using a 5 v reference, the recommended reference devices are the adr445 , adr435 , or adr425 ; when using 2.5 v, the adr441 , adr431 , or adr421 are recommended. the voltage applied to the reference input (v ref+ ) operates both as a reference supply and as a power supply to the AD7767/AD7767-1/AD7767-2 device. therefore, when using a 5 v reference input, the full-scale differential input range of the AD7767/AD7767-1/AD7767-2 is 10 v. see the driving the AD7767 section for details on the maximum input voltage.
AD7767 rev. c | page 17 of 24 AD7767 interface the AD7767 provides the user with a flexible serial interface, enabling the user to implement the most desirable interfacing scheme for their application. the AD7767 interface comprises seven different signals. five of these signals are inputs: mclk, cs , sync / pd , sclk, and sdi. the other two signals are outputs: drdy and sdo. initial power-up on initial power-up, apply a continuous mclk signal. it is recommended that the user reset the AD7767 to clear the filters and ensure correct operation. the reset is completed as shown in figure 5 , with all events occurring relative to the rising edge of mclk. a negative pulse on the sync / pd input initiates the reset, and the drdy output switches to logic high and remains high until valid data is available. following the power-up of the AD7767 by transitioning the sync / pd pin to logic high, a settling time is required before valid data is output by the device. this settling time, t settling , is a function of the mclk frequency and the decimation rate. lists the settling time of each AD7767 model and should be referenced when reviewing . table 7 figure 5 table 7. filter settling time after sync / pd model decimation rate t settling 1 AD7767 8 (594 t mclk ) + t 21 AD7767-1 16 (1186 t mclk ) + t 21 AD7767-2 32 (2370 t mclk ) + t 21 1 t settling is measured from the first mclk rising edge after the rising edge of sync / pd to the falling edge of drdy . reading data the AD7767 outputs its data conversion results in an msb-first, twos complement, 24-bit format on the serial data output pin (sdo). mclk is the master clock, which controls all the AD7767 conversions. the sclk is the serial clock input for the device. all data transfers take place with respect to the sclk signal. the drdy line is used as a status signal to indicate when the data is available to be read from the AD7767. the falling edge of drdy indicates that a new data-word is available in the output register of the device. drdy stays low during the period that output data is permitted to be read from the sdo pin. the drdy signal returns to logic high to indicate when not to read from the device. ensure that a data read is not attempted during this period while the output register is being updated. the AD7767 offers the option of using a chip select input signal ( cs ) in its data read cycle. the cs signal is a gate for the sdo pin and allows many AD7767 devices to share the same serial bus. it acts as an instruction signal to each of these devices indicating permission to use the bus. when cs is logic high, the sdo line of the AD7767 is tristated. there are two distinct patterns that can be initiated to read data from the AD7767 device: a pattern for when the cs falling edge occurs after the drdy falling edge and a pattern for when the cs falling edge occurs before the drdy falling edge (when cs is set to logic low). when the cs falling edge occurs after the drdy falling edge, the msb of the conversion result is available on the sdo line on the cs falling edge. the remaining bits of the conversion result (msb ? 1, msb ? 2, and so on) are clocked onto the sdo line by the falling edges of sclk that follow the cs falling edge. details this interfacing scheme. figure 3 when cs is tied low, the AD7767 serial interface can operate in 3-wire mode as shown in . in this case, the msb of the conversion result is available on the sdo line on the falling edge of figure 4 drdy . the remaining bits of the data conversion result (msb ? 1, msb ? 2, and so on) are clocked onto the sdo line by the subsequent sclk falling edges. power-down, reset, and synchronization the AD7767 sync / pd pin allows the user to synchronize multiple AD7767 devices. this pin also allows the user to reset and power down the AD7767 device. these features are implemented relative to the rising edges of mclk and are shown in , marked as a, b, c, and d. figure 5 to power down, reset, or synchronize a device, the AD7767 sync / pd pin should be taken low. on the first rising edge of mclk, the AD7767 is powered down. the drdy pin transi- tions to logic high, indicating that the data in the output register is no longer valid. the status of the sync / pd pin is checked on each subsequent rising edge of mclk. on the first rising edge of mclk after the sync / pd pin is taken high, the AD7767 is taken out of power-down. on the next rising edge, the filter of the AD7767 is reset. on the following rising edge, the first new sample is taken. a settling time, t settling , from the filter reset must elapse before valid data is output by the device (see tabl e 7 ). the drdy output goes logic low after t settling to indicate when valid data is available on sdo for readback.
AD7767 rev. c | page 18 of 24 daisy chaining daisy chaining devices allows numerous devices to use the same digital interface lines by cascading the outputs of multiple adcs on a single data line. this feature is especially useful for reduc- ing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a shift register where data is clocked on the falling edge of sclk. the block diagram in figure 36 shows how devices must be connected to achieve daisy-chain functionality. the scheme shown operates by passing the output data of the sdo pin of an AD7767 device to the sdi input of the next ad 7767 device in the chain. the data then continues through the chain until it is clocked onto the sdo pin of the first device in the chain. reading data in daisy-chain mode an example of a daisy chain of four AD7767 devices is shown in figure 36 and figure 37 . in the case illustrated in figure 36 , the output of the AD7767 labeled a is the output of the full daisy chain. the last device in the chain (the AD7767 labeled d) has its serial data input (sdi) pin connected to ground. all the devices in the chain must use common mclk, sclk, cs , and sync / pd signals. to enable the daisy-chain conversion process, apply a common sync / pd pulse to all devices, synchronizing all the devices in the chain (see the section). power-down, reset, and synchronization after applying a sync / pd pulse to all the devices, there is a delay (as listed in ) before valid conversion data appears at the output of the chain of devices. as shown in , the first conversion result is output from the AD7767 device labeled a. this 24-bit conversion result is followed by the conversion results from the devices labeled b, c, and d, respectively, with all conversion results output in an msb-first sequence. the stream of conversion results is clocked through each device in the chain and is eventually clocked onto the sdo pin of the AD7767 device labeled a. the conversion results of all the devices in the chain must be clocked onto the sdo pin of the final device in the chain while its table 7 figure 37 drdy signal is active low. this is illustrated in the examples shown ( and ), where the conversion results from the devices labeled a, b, c, and d are clocked onto sdo (a) during the time between the falling edge of figure 37 figure 38 drdy (a) and the rising edge of drdy (a). choosing the sclk frequency as shown in figure 37 , the number of sclk falling edges that occur during the period when drdy (a) is active low must match the number of devices in the chain multiplied by 24 (the number of bits that must be clocked through onto sdo (a) for each device). the period of sclk (t sclk ) required for a known daisy-chain length using a known common mclk frequency must, therefore, be established in advance. note that the maximum sclk frequency is governed by t 8 and is specified in the timing specifications table for different v drive voltages. in the case where cs is tied logic low, ? ? ? ? ? ? k t t read sclk 24 (1) where: k is the number of AD7767 devices in the chain. t sclk is the period of the sclk. t read equals t drdy ? t 5 . in the case where cs is used in the daisy-chain interface, ( ) ( ) ? ? ? ? ? ? ++? k tttt t 1376 read sclk 24 (2) where: k is the number of AD7767 devices in the chain. t sclk is the period of the sclk. t read equals t drdy ? t 5 . note that the maximum value of sclk is governed by t 8 and is specified in the timing specifications table for different v drive voltages.
AD7767 rev. c | page 19 of 24 daisy-chain mode configuration and timing diagrams 06859-013 sync/pd mclk cs sdi sdi sdo sclk AD7767 (d) sclk cs sync/pd sync/pd mclk cs sdi sdo sclk AD7767 (c) sync/pd mclk cs sdi sdo sclk AD7767 (b) sync/pd mclk cs sdi sdo drdy sclk AD7767 (a) mclk figure 36. daisy-chai n configuration with four AD7767 devices 06859-014 mclk drdy (a) sclk sdo (a) sdi (a) = sdo (b) sdi (b) = sdo (c) sdi (c) = sdo (d) cs 1 8 n AD7767 (a) AD7767 (b) AD7767 (c) AD7767 (d) AD7767 (a) AD7767 (b) AD7767 (c) AD7767 (d) AD7767 (b) AD7767 (c) AD7767 (d) AD7767 (c) AD7767 (d) AD7767 (d) 24 t sclk 24 t sclk 24 t sclk 24 t sclk figure 37. daisy-chain timing diagram (n = 1 for AD7767, n = 2 for AD7767-1, n = 4 for AD7767-2) when driving the AD7767 06859-015 mclk sdo (a) sdi (a) = sdo (b) sclk drdy (a) cs msb (a) lsb (a) msb (b) lsb (b) lsb (c) msb (c) msb (b) lsb (b) msb (c) lsb (c) lsb (d) msb (d) 1 t 16 t 17 figure 38. daisy-chain sdi setup and hold timing
AD7767 rev. c | page 20 of 2 4 driving the AD7767 r1 and r2 set the attenuation ratio between the input range and the adc range (v ref ). r1, r2, and c f are chosen depending on the desired input resistance, signal bandwidth, antialiasing, and noise contribution. the ratio of r2 to r1 should be equal to the ratio of ref to the peak-to-peak input voltage. for example, for the 10 v range with a 4 k impedance, r2 = 1 k and r1 = 4 k. the AD7767 must be driven with fully differential inputs. the common-mode voltage of the differential inputs to the AD7767 device and therefore the limits on the differential inputs are set by the reference voltage (v ref ) applied to the device. the common- mode voltage of the AD7767 is v ref /2. when the AD7767 v ref+ pin has a 5 v supply (using adr445 , adr435 , or adr425 ), the common mode is at 2.5 v, meaning that the maximum inputs that can be applied on the AD7767 differential inputs are a 5 v p-p input around 2.5 v. r3 and r4 set the common mode on the in? input, and r5 and r6 set the common mode on the in+ input of the adc. the common mode, which is equal to the voltage present at v offset1 , should be close to v ref /2. the voltage present should roughly be set to the ratio of v offset1 to 1 + r2/r1. 06859-016 0v v in+ v in? v ref v ref 2 0v v ref v ref 2 06859-020 ada4841-1 15 ? 3.3nf 1k? ada4841-1 15 ? 3.3nf 1k? 4 5 1 2 AD7767 av dd v ref+ v in+ v in? 2.2nf 2.2nf * adr4xx adp3330-2.5 2.5v 2.5v to 5v reference voltage 1k? 1k? 1k? 1k? ain+ ain? *see v ref+ input signal section for details. figure 39. maximum differential inputs to the AD7767 an analog voltage of 2.5 v supplies the AD7767 av dd pin. however, the AD7767 allows the user to apply a reference voltage of up to 5 v. this provides the user with an increased full-scale range, offering the user the option of using the AD7767 with a greater lsb voltage. figure 39 shows the maximum inputs to the AD7767. figure 40. driving the AD7767 from a fully differential source 15 ? 15 ? 100f r1 100nf 100nf 2.5v vout = 5v ref 5.2v ?0.2v c f r4 r2 r6 vin r3 r5 v ref+ av dd agnd v in+ v in? AD7767 2.2nf 2.2nf ada4941 in fb outp outn ref voffset1 voffset2 adr425 adr445 v in adp3330-2.5 ldo dgnd 0.1f 0.1f 06859-018 differential signal source an example of recommended driving circuitry that can be used in conjunction with the AD7767/AD7767-1/AD7767-2 is shown in figure 40 . figure 40 shows how the ada4841-1 device can be used to drive an input to the AD7767/AD7767-1/AD7767-2 from a differential source. each of the differential paths is driven by an ada4841-1 device. single-ended signal source for applications using a single-ended analog signal, either bipolar or unipolar, the ada4941-1 single-ended-to-differential driver creates a fully differential input to the AD7767/AD7767-1/ AD7767-2. the schematic is shown in figure 41 . figure 41. driving the AD7767 from a single-ended source table 8. resistor values required when using the differential to single-ended circuit with ada4941 (see figure 41 ) v in (v) v offset1 (v) v offset2 (v) out+ (v) out? (v) r1 (k) r2 (k) r4 (k) r3 = r5 = r6 (k) +20, ?20 2.5 2.203 ?0.01, +4.96 5.01, 0.04 8.06 1 12.7 10 +10, ?10 2.5 2.000 0.01, 4.99 4.99, 0.01 4.02 1 15 10 +5, ?5 2.5 1.667 0.00, 5.00 5.00, 0.00 2 1 20 10
AD7767 rev. c | page 21 of 2 4 antialiasing the AD7767/AD7767-1/AD7767-2 sample the analog input at a maximum rate of 1.024 mhz. the on-board digital filter provides up to 100 db attenuation for any possible aliasing frequency in the range from the beginning of the filter stop band (0.547 odr) to where the image of the digital filter pass band occurs. this occurs at mclk minus the filter stop band (mclk ? 0.547 odr), as shown in figure 42 . 06859-231 digital filter 100db antialias protection f mclk band of interest f mclk ? (0.547 odr) first image point digital filter image at f mclk figure 42. AD7767/AD7767-1/AD7767 spectrum table 9 shows the attenuation achieved by various orders of front-end antialias filters prior to the signal entering the AD7767/ AD7767-1/AD7767-2 at the image of the digital filter stop band, which is 1.024 mhz ? 0.547 odr. table 9. antialias filter order, attenuation at at first image point model filter order attenuation at 1.024 mhz C 0.547 odr AD7767 first 27 db second 50 db third 70 db AD7767-1 first 33 db second 62 db third 89 db AD7767-2 first 38 db second 74 db third 110 db the ad7764 and ad7765 - devices are available to customers that require extra antialias protection. these devices sample the signal internally at a rate of 20 mhz to achieve up to a maximum of 156 khz or 312 khz output data rate. this means that the first alias point of these devices when run at the maximum speeds is 19.921 mhz and 19.843 mhz, respectively. power dissipation the AD7767/AD7767-1/AD7767-2 offer exceptional perform- ance at ultralow power. figure 43 , figure 44 , and figure 45 show how the current consumption of the AD7767/AD7767-1/ AD7767-2 scales with the mclk frequency applied to the device. both the digital and analog currents scale as the mclk frequency is reduced. the actual throughput equals the mclk frequency applied divided by the decimation rate employed by the device in use. for instance, operating the AD7767 device with an mclk of 800 khz results in an output data rate of 100 khz due to the decimate-by-8 filtering. 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 1000k 900k 800k 700k 600k 500k 400k 300k 200k 100k current (ma) frequency (hz) 06859-226 i ref ai dd di dd figure 43. AD7767 current vs. mclk frequency 2.5 2.0 1.5 1.0 0.5 0 0 1000k 900k 800k 700k 600k 500k 400k 300k 200k 100k current (ma) frequency (hz) 06859-227 i ref ai dd di dd figure 44. AD7767-1 current vs. mclk frequency 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 1000k 900k 800k 700k 600k 500k 400k 300k 200k 100k current (ma) frequency (hz) 06859-228 i ref ai dd di dd figure 45. AD7767-2 current vs. mclk frequency
AD7767 rev. c | page 22 of 2 4 v ref+ input signal the AD7767/AD7767-1/AD7767-2 v ref + pin is supplied with a voltage in the range of 2.4 v to 2 av dd (nominally 5 v). it is recommended that the v ref+ input be generated by a low noise voltage reference. examples of such references are the adr445 , adr435 , adr425 (5 v output), and adr421 (2.5 v output). typical reference supply circuits are shown in figure 46 . the reference voltage input pin (v ref+ ) also acts as a power supply to the AD7767/AD7767-1/ AD7767-2 device. for a 5 v v ref+ input, a full-scale input of 5 v on both v in+ and v in? can be applied while voltage supplies to pins av dd remain at 2.5 v. this configuration reduces the number of different supplies required. the output of the low noise voltage reference does not require a buffer; however, decoupling the output of the low noise reference is important. place a 0.1 f capacitor at the output of the voltage reference devices ( adr445 , adr435 , adr425 , and adr421 ) and follow the decoupling advice provided for the reference device chosen. as mentioned, the nominal supply to the v ref+ pin is 5 v to achieve the full dynamic range available. when a 2.5 v v ref+ input is used (that is, in low power applications), the signal-to- noise ratio and dynamic range figures (generated using a 5 v v ref+ input) quoted in the specifications section decrease by 6 db, a direct result of halving the available input range. the AD7767/AD7767-1/AD7767-2 device requires a 100 f capacitor to ground, which acts as a decoupling capacitor and as a reservoir of charge for the v ref+ pin. place this capacitor as close to the AD7767/AD7767-1/AD7767-2 device as possible. reducing the value of this capacitor (c40 in figure 46 ) to 10 f typically degrades noise performance by 1 db. c40 can be an electrolytic or tantalum capacitor. c40 100f c39 0.1f c35 0.1f c34 10f reference supply v+ v ref+ v out v in 06859-021 AD7767/ AD7767-1/ AD7767-2 adr4xx figure 46. AD7767/AD7767-1/AD7767-2 reference input configuration multiplexing analog input channels the AD7767/AD7767-1/AD7767-2 can be used with a multi- plexer configuration. as per any converter that uses a digital filtering block, the maximum switching rate or the output data rate per channel is a function of the digital filter settling time. a user multiplexing the analog inputs to a converter that employs a digital filter must wait the full digital filter settling time before a valid conversion result can be achieved; after this settling time, the channel can be switched. then, the full settling time must again be observed before a valid conversion result is available and the input is switched once more. the AD7767 filter settling time equals 74 divided by the output data rate in use. the maximum switching frequency in a multiplexed application is, therefore, 1/(74/odr), where the output data rate (odr) is a function of the applied mclk frequency and the decimation rate employed by the device in question. for example, applying a 1.024 mhz mclk frequency to the AD7767 results in a maximum output data rate of 128 khz, which in turn allows a 1.729 khz multiplexer switching rate. the AD7767-1 and the AD7767-2 employ digital filters with longer settling time to achieve greater precision; thus, the maximum switching frequency for these devices is 864 hz and 432 hz, respectively.
AD7767 rev. c | page 23 of 2 4 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 47. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD7767bruz ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 AD7767bruz-rl7 ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 AD7767bruz-1 ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 AD7767bruz-1-rl7 ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 AD7767bruz-2 ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 AD7767bruz-2-rl7 ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 eval-AD7767edz evaluation board eval-AD7767-1edz evaluation board eval-AD7767-2edz evaluation board eval-ced1z converter evaluation and development board 1 z = rohs compliant part.
AD7767 rev. c | page 24 of 24 notes ?2007C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d06859-0-5/10(c)

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